This invention relates to pulse frequency division and more particularly, to an arrangement for frequency division by N/2 where N is an odd integer other than one.
In C. W. Pugh U.S. Pat. No. 3,189,832, issued June 15, 1965, there is shown an arrangement for N/2 pulse frequency division which employs a modulo N+1 counter. The output pulse of the counter is derived by utilizing AND gates that are enabled when a particular count is reached. By making available both the input signal and its inverse to the counter, the output pulse may be made to appear either during the first half or during the second half of a pulse period. In that patent the approach taken is to employ a first decoding AND gate to yield an output pulse during the first half of the first pulse period and a second such AND gate to trigger a one-shot multivibrator during the second half of the [(N+1)/2].sup.th pulse period. The operated one-shot multivibrator, in turn, produces a second output pulse and in addition causes the counter to prematurely advance its count by one. Thereafter, the counter continues to advance to N+1 and then recycles. Thus, in this approach a count of N+1 is achieved in N pulse periods and results in two equally spaced output pulses.
While the above-described frequency division arrangement appears to be satisfactory for a given input pulse frequency, its general applicability is somewhat limited. The maximum repetition rate of the incoming pulse signal is limited by the need of the one-shot multivibrator to return to a stable state after each input pulse. It would, therefore, be desirable to provide an N/2 frequency divider that is independent of the frequency of the input signal.
A frequency divider that does not use a one-shot multivibrator or any other delay element has been described in the prior art U.S. Pat. No. 3,571,728 of J. J. Andrea et al., issued Mar. 23, 1971. In that arrangement two modulo N counters are employed so that the output pulse of any given counter occurs exactly between two consecutive output pulses of the other counter. Synchronism is maintained between the two counters by causing the first counter, when it achieves a count of (N+1)/2, to reset the second counter. The output pulse of the divider occurs when neither of the output levels of the counters is high.
While this arrangement overcomes the abovementioned frequency dependency problem, its design requires at least 2(log.sub.2 N) flip-flops. It would be useful to provide an N/2 frequency divider whose operation is frequency independent and whose design significantly reduces from 2(log.sub.2 N) the number of flip-flops required.